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Freescale Semiconductor /MKM34Z7 /NVIC /NVIC_ISPR

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Interpret as NVIC_ISPR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)SETPEND0 0 (0)SETPEND1 0 (0)SETPEND2 0 (0)SETPEND3 0 (0)SETPEND4 0 (0)SETPEND5 0 (0)SETPEND6 0 (0)SETPEND7 0 (0)SETPEND8 0 (0)SETPEND9 0 (0)SETPEND10 0 (0)SETPEND11 0 (0)SETPEND12 0 (0)SETPEND13 0 (0)SETPEND14 0 (0)SETPEND15 0 (0)SETPEND16 0 (0)SETPEND17 0 (0)SETPEND18 0 (0)SETPEND19 0 (0)SETPEND20 0 (0)SETPEND21 0 (0)SETPEND22 0 (0)SETPEND23 0 (0)SETPEND24 0 (0)SETPEND25 0 (0)SETPEND26 0 (0)SETPEND27 0 (0)SETPEND28 0 (0)SETPEND29 0 (0)SETPEND30 0 (0)SETPEND31

SETPEND29=0, SETPEND23=0, SETPEND12=0, SETPEND27=0, SETPEND26=0, SETPEND20=0, SETPEND14=0, SETPEND13=0, SETPEND7=0, SETPEND31=0, SETPEND17=0, SETPEND8=0, SETPEND5=0, SETPEND25=0, SETPEND24=0, SETPEND3=0, SETPEND4=0, SETPEND28=0, SETPEND15=0, SETPEND2=0, SETPEND10=0, SETPEND22=0, SETPEND21=0, SETPEND30=0, SETPEND0=0, SETPEND16=0, SETPEND9=0, SETPEND18=0, SETPEND11=0, SETPEND1=0, SETPEND19=0, SETPEND6=0

Description

Interrupt Set Pending Register

Fields

SETPEND0

DMA channel 0 transfer complete interrupt set-pending bit

0 (0): write: no effect; read: DMA channel 0 transfer complete interrupt is not pending

1 (1): write: changes the DMA channel 0 transfer complete interrupt state to pending; read: DMA channel 0 transfer complete interrupt is pending
SETPEND1

DMA channel 1 transfer complete interrupt set-pending bit

0 (0): write: no effect; read: DMA channel 1 transfer complete interrupt is not pending

1 (1): write: changes the DMA channel 1 transfer complete interrupt state to pending; read: DMA channel 1 transfer complete interrupt is pending
SETPEND2

DMA channel 2 transfer complete interrupt set-pending bit

0 (0): write: no effect; read: DMA channel 2 transfer complete interrupt is not pending

1 (1): write: changes the DMA channel 2 transfer complete interrupt state to pending; read: DMA channel 2 transfer complete interrupt is pending
SETPEND3

DMA channel 3 transfer complete interrupt set-pending bit

0 (0): write: no effect; read: DMA channel 3 transfer complete interrupt is not pending

1 (1): write: changes the DMA channel 3 transfer complete interrupt state to pending; read: DMA channel 3 transfer complete interrupt is pending
SETPEND4

Serial Peripheral Interface 0/1 interrupt set-pending bit

0 (0): write: no effect; read: Serial Peripheral Interface 0/1 interrupt is not pending

1 (1): write: changes the Serial Peripheral Interface 0/1 interrupt state to pending; read: Serial Peripheral Interface 0/1 interrupt is pending
SETPEND5

Programmable Delay Block 0 interrupt set-pending bit

0 (0): write: no effect; read: Programmable Delay Block 0 interrupt is not pending

1 (1): write: changes the Programmable Delay Block 0 interrupt state to pending; read: Programmable Delay Block 0 interrupt is pending
SETPEND6

Low-voltage detect, low-voltage warning interrupt set-pending bit

0 (0): write: no effect; read: Low-voltage detect, low-voltage warning interrupt is not pending

1 (1): write: changes the Low-voltage detect, low-voltage warning interrupt state to pending; read: Low-voltage detect, low-voltage warning interrupt is pending
SETPEND7

Quad Timer Channel 0 interrupt set-pending bit

0 (0): write: no effect; read: Quad Timer Channel 0 interrupt is not pending

1 (1): write: changes the Quad Timer Channel 0 interrupt state to pending; read: Quad Timer Channel 0 interrupt is pending
SETPEND8

Quad Timer Channel 1 interrupt set-pending bit

0 (0): write: no effect; read: Quad Timer Channel 1 interrupt is not pending

1 (1): write: changes the Quad Timer Channel 1 interrupt state to pending; read: Quad Timer Channel 1 interrupt is pending
SETPEND9

Quad Timer Channel 2 interrupt set-pending bit

0 (0): write: no effect; read: Quad Timer Channel 2 interrupt is not pending

1 (1): write: changes the Quad Timer Channel 2 interrupt state to pending; read: Quad Timer Channel 2 interrupt is pending
SETPEND10

Quad Timer Channel 3 interrupt set-pending bit

0 (0): write: no effect; read: Quad Timer Channel 3 interrupt is not pending

1 (1): write: changes the Quad Timer Channel 3 interrupt state to pending; read: Quad Timer Channel 3 interrupt is pending
SETPEND11

PIT0/PIT1 interrupt set-pending bit

0 (0): write: no effect; read: PIT0/PIT1 interrupt is not pending

1 (1): write: changes the PIT0/PIT1 interrupt state to pending; read: PIT0/PIT1 interrupt is pending
SETPEND12

Low Leakage Wakeup interrupt set-pending bit

0 (0): write: no effect; read: Low Leakage Wakeup interrupt is not pending

1 (1): write: changes the Low Leakage Wakeup interrupt state to pending; read: Low Leakage Wakeup interrupt is pending
SETPEND13

Command complete and read collision interrupt set-pending bit

0 (0): write: no effect; read: Command complete and read collision interrupt is not pending

1 (1): write: changes the Command complete and read collision interrupt state to pending; read: Command complete and read collision interrupt is pending
SETPEND14

CMP0/CMP1/CMP2 interrupt set-pending bit

0 (0): write: no effect; read: CMP0/CMP1/CMP2 interrupt is not pending

1 (1): write: changes the CMP0/CMP1/CMP2 interrupt state to pending; read: CMP0/CMP1/CMP2 interrupt is pending
SETPEND15

Segment LCD interrupt set-pending bit

0 (0): write: no effect; read: Segment LCD interrupt is not pending

1 (1): write: changes the Segment LCD interrupt state to pending; read: Segment LCD interrupt is pending
SETPEND16

Analog-to-Digital Converter interrupt set-pending bit

0 (0): write: no effect; read: Analog-to-Digital Converter interrupt is not pending

1 (1): write: changes the Analog-to-Digital Converter interrupt state to pending; read: Analog-to-Digital Converter interrupt is pending
SETPEND17

PORTA,PORTB,PORTC,PORTD,PORTE,PORTF,PORTH,PORTI,PORTJ,PORTK,PORTL,PORTM interrupt set-pending bit

0 (0): write: no effect; read: PORTA,PORTB,PORTC,PORTD,PORTE,PORTF,PORTH,PORTI,PORTJ,PORTK,PORTL,PORTM interrupt is not pending

1 (1): write: changes the PORTA,PORTB,PORTC,PORTD,PORTE,PORTF,PORTH,PORTI,PORTJ,PORTK,PORTL,PORTM interrupt state to pending; read: PORTA,PORTB,PORTC,PORTD,PORTE,PORTF,PORTH,PORTI,PORTJ,PORTK,PORTL,PORTM interrupt is pending
SETPEND18

RNGA interrupt set-pending bit

0 (0): write: no effect; read: RNGA interrupt is not pending

1 (1): write: changes the RNGA interrupt state to pending; read: RNGA interrupt is pending
SETPEND19

UART0/UART1/UART2/UART3 interrupt set-pending bit

0 (0): write: no effect; read: UART0/UART1/UART2/UART3 interrupt is not pending

1 (1): write: changes the UART0/UART1/UART2/UART3 interrupt state to pending; read: UART0/UART1/UART2/UART3 interrupt is pending
SETPEND20

Memory Mapped Arithmetic Unit interrupt set-pending bit

0 (0): write: no effect; read: Memory Mapped Arithmetic Unit interrupt is not pending

1 (1): write: changes the Memory Mapped Arithmetic Unit interrupt state to pending; read: Memory Mapped Arithmetic Unit interrupt is pending
SETPEND21

AFE Channel 0 interrupt set-pending bit

0 (0): write: no effect; read: AFE Channel 0 interrupt is not pending

1 (1): write: changes the AFE Channel 0 interrupt state to pending; read: AFE Channel 0 interrupt is pending
SETPEND22

AFE Channel 1 interrupt set-pending bit

0 (0): write: no effect; read: AFE Channel 1 interrupt is not pending

1 (1): write: changes the AFE Channel 1 interrupt state to pending; read: AFE Channel 1 interrupt is pending
SETPEND23

AFE Channel 2 interrupt set-pending bit

0 (0): write: no effect; read: AFE Channel 2 interrupt is not pending

1 (1): write: changes the AFE Channel 2 interrupt state to pending; read: AFE Channel 2 interrupt is pending
SETPEND24

AFE Channel 3 interrupt set-pending bit

0 (0): write: no effect; read: AFE Channel 3 interrupt is not pending

1 (1): write: changes the AFE Channel 3 interrupt state to pending; read: AFE Channel 3 interrupt is pending
SETPEND25

IRTC interrupt interrupt set-pending bit

0 (0): write: no effect; read: IRTC interrupt interrupt is not pending

1 (1): write: changes the IRTC interrupt interrupt state to pending; read: IRTC interrupt interrupt is pending
SETPEND26

I2C0/I2C1 interrupt set-pending bit

0 (0): write: no effect; read: I2C0/I2C1 interrupt is not pending

1 (1): write: changes the I2C0/I2C1 interrupt state to pending; read: I2C0/I2C1 interrupt is pending
SETPEND27

LPUART0 status and error interrupt set-pending bit

0 (0): write: no effect; read: LPUART0 status and error interrupt is not pending

1 (1): write: changes the LPUART0 status and error interrupt state to pending; read: LPUART0 status and error interrupt is pending
SETPEND28

Multipurpose Clock Generator interrupt set-pending bit

0 (0): write: no effect; read: Multipurpose Clock Generator interrupt is not pending

1 (1): write: changes the Multipurpose Clock Generator interrupt state to pending; read: Multipurpose Clock Generator interrupt is pending
SETPEND29

EWM/WDOG interrupt set-pending bit

0 (0): write: no effect; read: EWM/WDOG interrupt is not pending

1 (1): write: changes the EWM/WDOG interrupt state to pending; read: EWM/WDOG interrupt is pending
SETPEND30

Low-Power Timer interrupt set-pending bit

0 (0): write: no effect; read: Low-Power Timer interrupt is not pending

1 (1): write: changes the Low-Power Timer interrupt state to pending; read: Low-Power Timer interrupt is pending
SETPEND31

XBAR interrupt set-pending bit

0 (0): write: no effect; read: XBAR interrupt is not pending

1 (1): write: changes the XBAR interrupt state to pending; read: XBAR interrupt is pending

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data